Arm has a great opportunity for a Package Design Engineer in our System-in-Package Integration team! You will work closely with IP, SoC Design, Package Design, Signal/Power Integrity and Systems teams throughout the company as well was interact with leading worldwide technology partners.
As we develop new system-level solutions for our world-class Arm IP ecosystems, packaging is a space where innovation is flourishing. This opportunity will focus on multichip systems where 2.xD and 3D approaches are necessary for optimizing performance.
Responsibilities:
The Package design engineer will be in charge of drawing novel System-in-Package designs. State of the art power delivery techniques and interfaces will be key in emerging technologies as advanced packaging is growing in industry importance.
The engineer will be responsible for the definition, design, and verification of package designs. Candidate will work closely with teams in France, US, UK, and other ARM locations on an as-needed basis. The candidate will interact with digital designers (P&R) on the inputs and constraints to build efficient designs, and also interact with SI/PI engineers. Clear communication with other team members is important.
This role will be a critical element of technology development, so the ability to work with loosely defined problems and adapt to changes is important.
The job will be based out of San Jose, CA or Chandler AZ location.
Required Skills and Experience:
· Engineering degree or equivalent
· 5 or more years of experience in package design
· Use an understanding of signal/power integrity principles to optimize designs
· Proficient in usage of package drawing tools (Cadence APD/SiP/Allegro or equivalent)
Nice to Have Skills:
· Experience with larger LPDDR and DDR interface
· Experience with 2.XD and 3D package systems