Job Description: In Arm's Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavour to deliver a quality silicon we need to ensure all our signoff checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improvising methodologies, influencing EDA tools and build a knowledge base which will help in our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If your interested in working with a team of collaborative and smart engineers responsible for validating RTL-to-Gate and Gate-to-GDS implementations, ensuring power intent correctness, and enabling high-quality silicon tapeout
Responsibilities:
- Synthesis, Physical design and implementation of Arm cores, systems and SoCs
- Ability to lead synthesis and constraints development , technical leadership
- Analyze design timing, area and power to help improve the quality of Arm IP.
- Develop and deploy new methodologies to improve implementation efficiency and results.
- Support and develop detailed implementation analysis and data-mining methodologies.
- Automation , Python knowledge and bringing in faster and efficient execution
- Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.
Required Skills and Experience :
- Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.
- 8+ years of proven experience in ASIC system-on-chip implementation flow from RTL to GDS.
- Experience in Timing Constraints development, Synthesis, Timing Closure
- Possess a high level of dedicated, initiative and problem-solving skills.
- Experience of tape outs of multi-million gate designs on latest technologies
- Ability to develop and work with timing constraints for build and signoff
- The ability to effectively work alone as well as in a team
- Ability to create trusting relationship and good work environment. Good professional attitude.
- LEC, CLP and ECO implementation knowledge to handle ECO cycles.
“Nice To Have” Skills and Experience :
- Experience with a wide range of programming, scripting & data presentation languages Eg. Tcl, Shell, Perl, Python.
- Experience with low power design techniques (power gating, voltage/frequency scaling).
- Experience with Verilog RTL design
- Understanding of DFT modes and their implications on Physical Design
- Learn quickly new flows and adapt to new developing environment.
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Accommodations at Arm
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Hybrid Working at Arm
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Equal Opportunities at Arm
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