Engineer - Physical design

Job Overview:

We are looking for a Physical Engineer specialized in building with 1–2 years of relevant experience to join our SoC implementation team. You will contribute to next-generation SoC projects, working across the synthesis-to-GDSII flow.

This role offers hands-on experience in physical implementation, timing analysis, debugging and power, performance and area (PPA) optimization. You will collaborate with design , verification, DFT and physical IP teams, using scripting and AI-assisted workflows to improve engineering efficiency.

Responsibilities:

• Complete and support RTL synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and GDSII generation with mentorship from senior engineers.

• Analyze and improve PPA through synthesis and physical implementation.

• Conduct static timing analysis with Synopsys PrimeTime, troubleshoot setup and hold violations, and assist in achieving timing closure across operating modes and corners.

• Review timing constraints, tool reports and implementation results to identify issues, investigate root causes and propose fixes.

• Assist with physical verification and final approval processes, including DRC, LVS, signal integrity, and EM/IR analysis.

• Develop Python and Tcl scripts to automate implementation tasks, analyze reports and track quality.

• Use approved AI tools and agents to assist with scripting, report analysis and debugging, while independently validating their outputs.

• Document results, communicate technical findings and collaborate with teams to resolve implementation issues.

Necessary Skills and Experience: 

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Microelectronics, VLSI or a related field.

• 1–2 years of relevant experience in ASIC/SoC physical design or implementation.

• Familiarity with the RTL-to-GDSII process, encompassing synthesis, floorplanning, placement, CTS, routing, and timing closure.

• Understanding of physical designfundamentals, including utilization, congestion, clock skew, latency, buffering and cell sizing.

• Hands-on experience with PrimeTime and at least one synthesis or physical implementation tools such as Fusion Compiler, Genus or Innovus.

• Knowledge of static timing analysis, including setup/hold checks, clock definitions, timing exceptions and multi-mode, multi-corner analysis.

• Ability to read Verilog RTL and gate-level netlists and trace timing paths to investigate implementation issues.

• Practical programming skills in Python, familiarity with Tcl, and confidence working in a Linux environment.

• Strong analytical and debugging skills, clear communication and a willingness to learn and take ownership of assigned tasks.

“Preferred” Skills and Experience: 

• Exposure to advanced-node, hierarchical implementation or large SoC integration.

• Familiarity with low-power concepts, UPF, multiple voltage domains, power gating and level shifters.

• Exposure to on-chip variation, timing derates, crosstalk and signal integrity.

• Basic knowledge of power distribution networks, EM/IR analysis, IO placement, and bump-planning considerations.

• Familiarity with DFT requirements and physical verification flows.

• Experience using AI coding assistants or agents for engineering automation, including effective task definition, output validation and responsible handling of proprietary build data.

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