Senior Principal SOC Power Lead

Job Overview:

We are seeking an experienced Senior Principal SOC Power Lead to drive power analysis, modeling, and optimization for System-on-Chip (SoC) solutions. This role will lead a small team of power engineers responsible for both pre- and post-silicon power convergence, working closely with architecture, design, verification, and product teams to achieve best-in-class power efficiency.

The ideal candidate will have extensive expertise in power analysis methodologies, SoC lifecycle flows, and multi-functional collaboration from architecture definition through productization.

Responsibilities:

As part of our Power Attainment team, yours is the opportunity for growth in understanding new use-cases, developing power modeling and crafting industry leading performance-per-watt solutions. We want your talents in promoting a culture of innovation, delivering on-time to product performance/power targets, and defining workflows to improve accuracy, turnaround time, and correlation to silicon.

Required Skills and Experience:

• Strong technical leadership with ability to develop accurate project plans involving multiple teams.

• Expertise in RTL and Netlist based power analysis and sign-off flows, EDA tools, and latest trends in SoC physical design and simulation/emulation use.

• Knowledge of ASIC design dependencies on power efficiency including technology node, mixed Vt design, standard cell and memory library selection, voltage, and power domain partitioning.

• Confirmed experience driving multiple projects and mentoring junior engineers.

• Verification experience in creating workload scenarios in simulation and emulation environments (e.g. VCS, Questasim, Incisive, Veloce Strato, Palladium, Zebu, etc).

• Excellent presentation, interpersonal and communication skills. Able to present technical content inside and outside of Arm.

“Nice To Have” Skills and Experience:

• Appreciation of software use-cases, benchmarks, and workloads and how they interact with hardware low power features like clock and power gating, voltage/frequency scaling, memory/logic retention

• Python for automation and modeling.

• SoC use-case power budget decomposition to IP power budget.